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Tissu 50% COTON 50% POLYESTER chaine & trame Retors, arm ure toile 1/1, 520g/m2, 150cm, traite 2i (imperimpu) Principales utilisations:cabas, bagagerie, tauds & voiles de vieux greem ents, baches, entoilages

The GS2971A is a multirate SDI integrated Receiver which includes complete SMPTE processing, as per SMPTE 425M, 292M and SMPTE 259MC. The SMPTE processing features can be bypassed to support signals with other coding schemes. The GS2971A integrates Gennum's adaptive cable equalizer technology, achieving unprecedented cable lengths and jitter tolerance. It features DC restoration to compensate for the DC content of SMPTE pathological signals. The device features an Integrated Reclocker with an internal VCO and a wide Input Jitter Tolerance (IJT) of 0.7UI. A serial digital loopthrough output is provided, which can be configured to output either reclocked or nonreclocked serial digital data. The serial digital output can be connected to an external cable driver. The device operates in one of four basic modes SMPTE mode, DVBASI mode, DataThrough mode or Standby mode.

Ultra-compact LTE Cat M1/Cat NB2 moduleLTE Cat M1/Cat NB2 module with ultra-low power consumption Compact SMT form factor ideal for size-constrained applications with tight space Super slim profile in LGA package Integrated RAM and Flash in baseband chipset Comprehensive set of hardware-based security features Fast time-to-market: reference designs, evaluation tools and timely technical support minimize design-in time and development efforts Robust mounting and interfaces Fast time-to-market:reference designs, evaluation tools and timely technical support minimize design-in time

Zur rechtwinkligen Verbindung von drei Aluminiumprofilen. Material:GD-ZN Farbe/Oberfläche:schwarz Gewicht:0,092 kg Nut:8

The EP103T LVDS transmitter supports transmission between the host and the flat panel display up to SXGA+ resolutions. The transmitter converts 25 bits (8bits/color, 2 dummy bits) of Low Voltage TTL data and 3 control bits into 4 LVDS (Low Voltage Differential Signal) data streams. At a maximum input clock rate of 135MHz, each LVDS differential data pair speed is 945Mbps, providing a total throughput of 3.78Gbps. The transmitter can be configured to input clock rising edge or falling edge strobe through an external pin. Support 10MHz to 135MHz clock rates for HVGA to SXGA+ resolution Up to 3.78Gbps bandwidth PLL requires no external components Cycletocycle jitter rejection 3.3V to 1.8V Low Voltage TTL tolerant Input Programmable data and control strobe select Power down mode supported

Compact Bi-Tec measurement device for the measurement of total luminous flux of single LEDs. Features: Cone-shaped measurement port with implemented integrating sphere, auxiliary lamp for substitution correction, spectral radiant power, color temperature, CRI, chromaticity coordinates, etc.